Part Number:BQ27532-G1
Dear all,
Has anyone got a default version of firmware for BQ27532-G1, in bq.fs?
Many thanks!
Sam
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BQ27532-G1: Default Firmware for BQ27532-G1 bqfs, dffs
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BQ2022A: Programming
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BQ25120A: BQ25120A : USB-C power delivery
Part Number:BQ25120A
Hi all
I'm working on a design with a BQ25120A battery charger and an USC Type C connector.
Charge seems ok with the following configuration :
- USB2 wall adapter,
- USB3 type C wall adapter without power delivery feature.
But a power delivery wall adapter doesn't provide any voltage when connected to by board.
in power delivery, we are not interested in high power, but to be compatible with maximum wall adapter.
The schematics is more or less the one of TIDA-00712.
Differential pair is connected to a STM32.
Thanks for your support.
Vincent
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TPS23754: TPS23754 Classification
Part Number:TPS23754
Dear Team,
My customer is facing the issue during classification.
But sometimes it works properly. Do you have any suggestions on it?
Attached schematic.
BR
Kevin
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BQ24172: Capacitor for battery
Part Number:BQ24172
As Ning mentioned in my another question , the total capacitance at the battery should not exceed 2200uF.
In my application, it will switch on and off of a load of about 22A, I would like to ask normally do I need to add a large electrolytic capacitor at the battery? It is because I have seen in some design there is a large (~680uF) electrolytic capacitor.
My battery is: 3-cells, 5000mAh, maximum 30C discharge.
Thank you very much!
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TPS65150: External VREF
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LM3478: lm3478
Part Number:LM3478
Dear all, what is the HS Code of this product ?
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TPS57060-Q1: Divider for Wide range Enable signal
Part Number:TPS57060-Q1
Hi Champs,
My customer would like to apply TPS57060-Q1 for Primary DCDC.
There are two input rails, Battery and IG, both rails have range from 10V to 32V as operating range, and 50V max.
IG rail is used to enable TPS57060-Q1, but the device doesn't have enough range as VIN port, divider circuitry would be required.
I attach the calculation as attached, could you check and suggest better solution?
Condition:
- IG input range : 10V to 32V as operation voltage, 50V for tolerance
- Assume if VEN >= 5.8V, internal zener sink 100uA through 10kohm built in resistance as shown in Figure 27.
- If VEN < 5.8V, VEN is defined by IG ,R1, and R2.
- VEN is set as 1.5V (with margin) when IG is 10V
Best regards,
(Please visit the site to view this file)
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BQ27421EVM-G1A: SCL or SDA rise time (tr) parameter + Rise time measurement level
Part Number:BQ27421EVM-G1A
Hello Texas Instruments,
I am the Component Engineer at Dexcom. We have two questions about the BQ27421EVM-G1A Fuel Gauge please. We are in the process of performing an urgent re-design, which is why we are asking these questions.
1. The SCL or SDA rise time (tr) is specified to be 300 ns maximum. What will happen if the rise time in our design is 400 ns? The other way to ask the question is how much margin do you have on this parameter? Do you have a histogram of data you have taken on this parameter?
2. The SCL or SDA rise time (tr) is specified to be 300 ns maximum. When you measured this parameter, did you use 10%/90% signal levels, or 20%/80% signal levels?
Thank you.
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TINA/Spice/TPS62263: Does TINA-TI model include control loop/compensation?
Part Number:TPS62263
Tool/software:TINA-TI or Spice Models
Does the TPS62263 model in TINA-TI model the control loop and compensation of the regulator? On my actual circuit, I see the voltage oscillate if the inductor is too large (presumable because the control loop is unstable), but I don't see this effect in TINA-TI simulation. I'm just wondering if that is something I should expect to see, or the model is simplified.
(Please visit the site to view this file)
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UCD9090-Q1: Watchdog function incorrect behavior
Part Number:UCD9090-Q1
Hello,
We are having an issue with the watchdog function of our UCD9090-Q1.
We have set it the watchdog timeout to 1ms and are toggling the WDI input every 900µs as depicted here below:
However, as you can see on the C2 channel, though we toggle at a higher rate than the 1ms, once in a while the WDO goes active (we have it set active high).
That is not exactly what we expected and we feel we followed the datasheet.
Our hypothesis on the issue is that the UCD samples the signal every 1ms and as we are not synchronized with it at all it sometimes happen that between two 1 ms intervals the WDI signal is seen by the UCD at the same level. If it is the case then we will most certainly have the issue wathever the timeout period we set (though less regularly if we set a higher period).
Clément
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UCD9090-Q1: State machine LGPO configuration understanding
Part Number:UCD9090-Q1
Hello,
We are trying to configure one of the LGPO of the UCD9090-Q1 in state machine mode and so far we didn't achieve to reach our objectives.
Basically what we are trying to achieve is the following:
- At power-up, our LGPO is expected to be at low level.
- We expect the LGPO to change as when one of the GPI goes high.
- Once it has changed due to the GPI, we expect it to change when one of the monitoring input goes in a power-good off state (which basically means our input power is gone).
We tried different configurations of both the AND PATH 1 and AND PATH 2 without luck.
Could you help us point how we should be configuring both AND PATH ?
Perhaps one of the misunderstanding comes from the initial state of the LGPO. Is the AND PATH 1 used AND PATH 2 when we go out of reset ?
Thanks,
Clément
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LP5018: The size of the thermal pad
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BQ76920: Cell Balancing issue with BQ7692003
Part Number:BQ76920
Customer has being seeing an issue with the below design. I will send NDA schematics once this thread is assigned.
The battery pack uses four 3.2V LiFePO4 cells. The product powered by the battery can draw maximum current of 20A.
Many of the issues we have had are now understood, however, we still have some problems with cell balancing.
So remaining questions are;
Does the design in the schematic have enough capability to balance cells which may have a attained a difference in SOC of perhaps 5-10%. Observing a pack with one cell in this condition shows that voltage on that cell rises quickly to 4.1V at the end of charge when others are still below 3.5 volts. With the internal balance enabled for that cell in the BQ7692003 management IC, it’s proving difficult to stop that cell triggering an over volt condition. (see enclosed PDF showing end of charge for a pack with a cell exhibiting this behavior).
Should we push over volt trigger above the 4.1V level we current have set ?
Should we allow charging to continue until remaining cells are closer to full charge ?
Should we just terminate charge when detecting this condition before reaching the over volt condition ?
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UCD90120A: GPO delay
Part Number:UCD90120A
We have an issue where we want to set a delay on the GPO assertion, but the actual response does not change.
The configuration is very simple, the GPIO3 of pin 13 is set as an output and is triggered by a GPI2 on pin 32. With no delay added to the assertion, GPIO3 asserts about 13ms after the GPI asserts. However, when a delay of 960 ms is configured and saved, the actual delay remains at 13 ms.
Below is the configuration window settings. Are we setting something wrong or forgetting a setting?
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Slope compensation for stable control loop
Hi,
A bit of an obscure question, but I will throw it out anyway:
In the TI document: Slup173 (Designing stable control loops). The equation for borderline stable slope compensation is given on page 17 as:
m3 = m2-m1/2 = Vi*Rs*(2*D-1)/2*Nt*L
My question is why is there a factor (2D-1)? By my reasoning:
m1= (Rs/Nt) dIs1/dt = (Rs/Nt)*(Vi-Vo)/L
m2= (Rs/Nt) dIs2/dt = (Rs/Nt)*(-Vo)/L
So m2-m1/2 = Vi*Rs/2*Nt*L.
Anyone familiar with this can clarify? Thanks
Mike
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UCD9090A: program loaded into flash
Part Number:UCD9090A
Hi,
When using the Fusion Power Designer GUI and the UCD90SEQ48EVM-560 eval board, we found that certain configurations are not present as seen on the Logic Controlled GPOs after the board is power cycled (and after the Store RAM to Flash button is selected in the GUI). The GPOs were showing the correct outputs after selecting the Write to Hardware button in the GUI. Could the wrong program be written to Flash? The STORE_DEFAULT_DONE BIT is set properly and there are no errors shown on the Status tab after the Store RAM to Flash button is selected.
We also found that certain simpler configurations are written to flash properly and work after the board is power cycled. Is there a limit to what can be written to flash regarding the complexity of the configuration of the logic controlled GPOs?
Could the GUI be optimizing out logic that it thinks is unnecessary?
One example of a configuration that did not work (outputs are low) after selecting Store RAM to Flash and power cycling the board is when one Logic Controlled GPO is dependent on the delayed output of another Logic Controlled GPO in order for it to be turned on:
GPO1 = GPI1 and (NOT)GPO2
GPO2 = (delayed 1ms upon assertion) GPO1
We used the GUI to find the checksum before and after power cycling the board and it matches. We also exported configuration files using the GUI and we can see the outputs are configured per those files.
Thank you,
Valerie
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LM5141: lm5141 in continius current mode (more 512 cycles) wihout hiccup(re-softstart) . It posssble?
Part Number:LM5141
Hi, can lm5141 work like lm5117 in continius current mode without hiccup(or re-softstart)?
Lm 5117 uses the RES pin : "The RES pin can also be configured for latch-off mode current limiting or non-hiccup mode cycle-by-cycle current limiting"
Does LM5141's RES pin have the same function?
And another question (lm4141) :
What will happen if in normal operation Vout increases (+10%) due to connection of an external power source (for example, a battery was connected) ? The Low Side mosfet will open and will stay open until the Vout is back to normal (or the mosfet is damaged ), or the bottom mosfet will stay open for one cycle, or something else?
Best Regards. Serj
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LM46002: Latch up Issue
Part Number:LM46002
Hello,
Our team from UK is here debugging a power supply board outsourced to Jabil. They are using an LM46002 simple switcher from a 22V DC input voltage to provide +15V and -15V outputs. They are preceded by a TPS2660 eFuse circuit. During startup, the eFuse circuit trips once or twice and then remains on. Sometimes, one or both of the simple switchers downstream get stuck in a latched-off condition. Do you know what might cause that to happen? Is there anything TI knows about an LM46002 IC becoming latched off? I think it might be in the internal Linear regulator circuit – perhaps if the “bias” input goes negative wrt pgnd. Any thoughts?
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UCC28070A: Replacing CT and Shunt with Hall Current Sensor
Part Number:UCC28070A
Has anyone attempted to replace the current transformer feedback in their switching converter designs with isolated hall current sensors or the like? Are there any non-obvious hazards with this approach?
Thanks!
Tony
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