TPS54620: Vsense lead length

Part Number:TPS54620

We have a design where it's better for us to put the TPS54620 on a daughter board, where the load (FPGA) is on the mother board. One approach is to use a bunch of pins on the connector between the boards to mitigate voltage drops. The other approach is to run the Vsense lead down the connector to the FPGA and use fewer pins on the connector. One engineer doesn't think that will work. How long can we run the pins between the Vsense pin to the load? Are there any considerations for the compensation network from the load to the Vsense pin?

Thanks.