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Cell PTC vs BMS voltage violation

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Hi folks,

Consider a 10S pack with 3V per cells.
Each cell has a builtin PTC with a lower trip current than what the BMS overcurrent protection is set to.
Apply a short between pack+ and pack-.
One PTC will kick in for sure.
The pack voltage will collapsed and split it in an uncontroller way depending on which PTC kicked in.
For example, if the 4th cell PTC kicks in, you end up with the following voltages at the top of each cell (1st cell neg terminal is ground):

c1: 3V
c2: 6V
c3: 9V
c4: -18V
c5: -15V
c6: -12V
c7: -9V
c8: -6V
c9: -3V
c10: ~0V (almost no current through a short)

This situation will for sure violate BMS IC specifications on most cell voltage sensing terminals.  Not to mention FETS and capacitors of any external balancing circuitry present.

I feel like a PTC kicking in would be a disaster.  Kind of paradoxical when you think that a PTC is meant to avoid a disaster..

Does anybody have an opinion on that?

Regards,

Frédéric


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