Part Number: LM5050-1
In my application, I have 2 power input module in the chassis, I decided to use LM5050 to prevent current reversal when another module attached to a backplane, on which there's already has a module on, the picture below is my test circuit in TINA-TI, I place a voltage controlled switch in between the 2 output of power module.
I am totally confused with the result:
1. Why the 12V_IN1/12V_IN2 ramp up sumultanously?
On a real board, the LM5050 do prevent the reversal conduction, and I have capture the in-rush current waveform on a real board, surprisingly, the current is very big compare capacitance on the output of the LM5050(C1/C4 in the test circuit) , from the waveform, the charges is estimated to be 112uC(44.8A * 5uS * 0.2), and capacitance of C1 or C4 is 9.3uF(charged to12V, and the Qg(total) of NMOS is 30nF), almost twice the actual capacitance, so
2. What's the other factors I need to count in when analysis the inrush current?
Thank you.
(PS: the encloures are the spice model for NMOS and TINA-TI circuit file FYI)
(Please visit the site to view this file)(Please visit the site to view this file)