Hello!
We have design a BMS circuit for a 14S battery pack based on BQ78350-BQ76940 chipset.
After assembling BMS circuits on battery packs in our production line, we experienced several failures (about 1-2% over some hundreds of products). In particular failed systems appear with FETs disabled, but there are no other evidences into registers map about any specific and wanted state (if we compare the registers map of a normal system with a failed one, only CHG and DSG flags into the Operation Status are different). These are two screenshot examples of a failed and normal systems:
Failures was observed into several steps of the battery pack assembly and in particular we found some of them after leaving systems at rest (before testing or also after finishing and sealing operations) or after the overcurrent test (in this latter case only the DSG FET was permanently into the off state, but no overcurrent protection flags were active).
By investigating on this problem we found some potential issues related on the alert pin.
On our board the alert pin is connected between the BQ76940 and BQ78350 by following a quite long path (our board has a particular form factor and it was very difficult to avoid this). A 470k pull-down resistor is connected very close to the BQ76940 pin, while a 1nF capacitor is connected quite close to the BQ73850 pin. During the design phase we used a 470k resistor because the 1M recommended value led to some problems (FETs permanently disabled) and also because a similar value were used into the "typical application" schematic.
Currently on the Alert pin we see different type of waveform, also on normally working systems:
- alert signal 1: continuous pulse train with increasing duty cycle
- alert signal 2: sequence of: 10s fixed low level, 3 pulses like above (each time the pulse duty cycle increases), about 10s fixed high level
We cannot understand why there are so different signals and which one is the correct one. Maybe both of them are ok (systems properly works in both cases), but it is strange to see so different situations.
Moreover we tried to recreate the failure by forcing a pull up (10k to 2.5V Vcc line) on the alert line, in order to simulate a disturb that can be coupled on such a line. Well, we observed two different reactions:
- if the pull-up in applied only for some second or for a few tens of seconds, FETs are only temporary disabled and they are enabled again after few instants after removing the pull up
- if the pull-up is applied for several tens of seconds (we don't know exactly the threshold value compared to the previous situation), the system enters into an halted state with FETs disabled and no evidence of any particular state into the registers map (except CHG and DSG flags disabled).
The latter one seems to be exactly the failure we experienced on our products. Unfortunately it is unrealistic on our products the Alert line was intentionally or accidentally pulled up for a so long time. So we would like to ask to any expert:
- is that correct there is a similar behavior if the Alert line is forced high?
- why there is a different behavior if the Alert line is forced high for a short or a long time?
- is it possible that a short disturb on such an Alert line can lead to a permanently halted situation with the only evidence of FETs off and no other information?
- if yes, is it possible to try to fix this problem by reducing the pull-down mounted resistor? which is the limit for the pull-down resistor?
- otherwise, could the 1nF capacitor create any critical situation? should we change it?
- more in general, do you have any idea or suggestion about the problem of our failures (also not related to the Alert pin)?
I hope in a kind prompt answer because we have to solve as soon as possible this problem.
Thank you very much for your support
Best regards
Matteo