Part Number: BQ76940EVM
After power on initialization, the DSG and CHG MOS are driven to close at a fixed time in the cycle, and these two states will be read in real time through interrupt. It is found that these two register bits will be pulled down abnormally as soon as they are pulled up (the same is true for TP10 and tp11 voltage of demo board through actual measurement).
The datasheet indicates that a specific fault will cause two drive bits to reset, but the status bits listed in the following table of sys_stat (0x00) are normal.
Check TS1 status, confirm that it does not enter ship mode, and confirm that S3 \ S4 and J14 are in normal status.
The following figure is a screenshot of the changes of DSG and CHG during the actual operation of my program for your reference.
Please help to analyze the reasons?