Part Number: EM1402EVM
To whom it may concern,
I am working on the design of a custom BMS based on EMB1499Q driver. I'm trying to simulate in LTSpice the forward converter used in EM1402EVM both in forward (charging cell) and in current-fed (discharging cell) mode. In order to simulate the driver signals I set timing constraints suggested in the datasheet SNOSCV7B.
Using the values indicated in the datasheet (128uH and n=1.14 and Cclamp=0.022uF) I see a different behaviour of the converter and ZVS condition seems not to be verified in the forward mode. So I set different values for the capacitor and the transformer in order to obtain good results (1.28uH n=1.14 Cclamp=2.2uF).
On the other hand when I simulate the current-fed mode (with values indicated above), when HS1 and HS2 driver signals are in overlap, there is an irregular current charging the Cds of LS MOS and discharging the Cds of HS1 MOS during the rising edge of the driver signal of HS1 MOS.
Please find attached the simulation files. Is there a condition that isn't satisfied?
Another problem is related to the use of the schmitt trigger inverter to emulate a turn on delay circuit for PWM_CLAMP signal:
The BU4S584G2 used in the schematic (EM1402EVM) provides a delay in both rising and falling edge of the input signal (PWM_CLAMP) but in the application it is recommanded to delay only the falling edge. Is the BU4S584G2 used to only set a delay on the falling edge?
Thank you very much in advance for the support.
Best Regards,
MP
Simulation files:
/cfs-file/__key/communityserver-discussions-components-files/196/Simulations.7z
Irregular current (Discharge):
/cfs-file/__key/communityserver-discussions-components-files/196/Irregular-current.pdf