I'm having an issue with figuring out the gain and offset correction of the BQ76925 and how it's being calculated in the Evaluation Softtware.
As far as I understand from the data-sheet the values are 5-bit 2's compliment number, except VREF OC which is 6-bit, which we'll ignore. To be negative, the high bit needs to be set just like an 8/16-bit 2's compliment . When looking at the software I see some positive and some negative values.
| Offset(mV) | Gain(0.1%) | |
| VREF_CAL | 3 | 0 |
| VC1_CAL | 0 | 1 |
| VC2_CAL | 1 | 0 |
| VC3_CAL | 1 | -1 |
| VC4_CAL | 1 | -1 |
| VC5_CAL | 1 | -3 |
| VC6_CAL | 3 | -6 |
The issue is when I read the EEPROM out the the I2C either myself or looking at the communications I don't every see the high bit being set. Looking at the comms log I see
I2C_R: 30 30 70
I2C_R: 31 01 CD
I2C_R: 32 10 C4
I2C_R: 33 1F C3
I2C_R: 34 1F 15
I2C_R: 35 1D 31
I2C_R: 36 3A BA
I2C_R: 37 04 2A
I2C_R: 38 00 B7
I2C_R: 3B 00 C9
Left number is the chip address + register (so 0x30 is is register 0x10). Middle number is the value, right number is CRC. Putting a scope on the I2C and the values I see on the scope match the software.
So all of the bits at address 0x18 (VC_CAL_EXT_2) and 0x1B (VREF_CAL_EXT) are 0, so I shouldn't be seeing any negative numbers on VC3/VC4/VC5/VC6. Also the datasheet says 0x1B bit 3 should always be 1, and it's obviously not.
Can anybody explain what's going on here? Is this a software bug and these should be positive values? VC3_GC and VC4_GC as +1.5% gain instead of -0.1%?
