Part Number:UCD3138
Customer is asking the status of the IO pin(used as an DPWM) before POR and after BOR, if the V33D has a slow slew rate?
↧
UCD3138: what is the status of IO pin of DPWM before POR and after BOR?
↧
UCC2895: Shut down when at Ta=70°C
Part Number:UCC2895
Hi，
Recently, during I debug UCC2895, the power system is OK at 25°C and -40°C, however, once the temperature is 70°C, output voltage begin to drop slowly form normal value. Then I mornitor the voltage of SS/DISB port, is drops from 5V to below 2.4V slowly, at that moment output voltage disappears. When temperature returns to normal, everything is OK. My condition is : RT=110kohm(IRT=27uA), FOSC=100KHz, VDD=12V.
I will appreciate for your reply, thanks very much.
↧
↧
TPS563200: TPS563200DDCR 6.0V Input 5.3V Output
Part Number:TPS563200
Dear All
We have a design including TPS563200DDCR
Parameters:
Vin: 5.7V~6.3V
Vout: 5.3V
With 6.0V At the input, we get 3.8V Output
We dont get 5.3VOutput Until input its 6.3V
↧
UCC28056: AC/DC 160W UCC28056 + UCC25630x for CoC V5 Tier 2
↧
BQ34Z100-G1: Available Energy counter wrapping
Part Number:BQ34Z100-G1
Hi,
I am faced with a strange behavior of the Available Energy counter, during battery charge only. The value seems to wrap, it suddenly becomes negative, then, most of the time, becomes positive again before the end of charge. Positive values are correct, even after the event. When the value goes negative, it keeps incrementing at the same pace, but with a large negative offset.
No problem during discharge.
Here are some logs showing the issue during learning cycles on various batteries. The wrapping event does not occur at the same time nor the same value of Available Energy. However it seems to disappear for lower battery capacities.
(Please visit the site to view this file)
(Please visit the site to view this file)
(Please visit the site to view this file)
(Please visit the site to view this file)
I have also extracted graphs on the word document below:
(Please visit the site to view this file)
All the learning cycles presented were successful.
I am using LiFePO4 cells with Chem ID 463, capacities range from 27Ah to 64Ah. Nominal cell voltage is 3.2V, Current are scaled by a factor of 4, and Energy scale is 2, seen from the gauge we thus have capacities ranging from 6750mAh to 16000mAh and energies ranging from 10800mWh to 25600mWh.
First hypothesis following a discussion with Bryan Kahler was a wrong value of the CC threshold parameter (still to its default value). However, setting the CC threshold to 90% of design capacity did not correct the issue.
Looking forward to your insights.
Best regards,
Jérémie
↧
↧
BQ25895: QON Control to exit shipment mode
Part Number:BQ25895
Hello,
We are working on battery operated device that uses BQ25895 battery charger. Since our major concern is on battery backup we are using shipment mode available in charger to prevent unnecessary power loss during standby mode.
According to datasheet we were able to enter into shipment mode with QON (with low of 10-12sec) in absence of VBUS.
Datasheet says "A logic high to low transition on QON pin with TSHIPMODE deglitch time(1sec) to enable BATFET to exit shipping mode"
If we hold QON low for 3 sec charger switches on BATFET for minimum of 1 sec and enters sleep mode.
What might be the issue here or how can we exit shipment mode without VBUS connected?
Thanks
↧
TINA/Spice/CSD88537ND: CSD88537ND high side & low side approximate power dissipation
Part Number:CSD88537ND
Tool/software:TINA-TI or Spice Models
Hi All,
can anyone please let me know the expected approximate power dissipation through high side & low side mosfets of CSD88537ND ?
Especially what would be the expected power dissipation through low side mosfet ideally ?
thank you
↧
What are the battery charger ICs and battery fuel gauges for the 3-cell lithium battery? The maximum charging current is 1A.
What are the battery charger ICs and battery fuel gauges for the 3-cell lithium battery? The maximum charging current is 1A.
↧
TPS2492: High voltage high output capacitance constant power load switching
Part Number:TPS2492
Hi,
I have been battling for some time now with a design using the TPS2492. Although the IC has both constant power and constant current control modes and is high voltage capable (which is why I opted for it initially), I have come to realise that my particular application seems to fall outside of its typical areas of application. However I think I have found a solution and I would like some feedback from the product experts to give me a little more confidence that the solution I have devised is indeed workable.
The problem occurs because I require to charge a large load capacitance and at a rather high voltage 62V Vin and Cout ~ 16mF. Clearly this cannot be done quickly and it is just impossible to find a MOSFET with the transient thermal impedance capable of withstanding a rapid charge, this is not to mention the required instantaneous currents required to achieve this. Therefore it is necessary to instead perform a slow power controlled charge at much much lower power levels <10W to allow the pass FET to dissipate the heat into a large heatsink (which is already part of my design anyway).
The conundrum which I faced still was that, in order to ensure that the power limit set-point is within the defined tolerances (PROG => 0.4V), I am forced to have a shunt Rsense which sets Ilim much lower than I actually require for the application.
I initially tried to use the alternative approach to charge control and tried a Dv/Dt capacitor loading the gate drive. This works exactly as expected but to ensure initial FET power limits are low enough when Vds is high, the charge time exceeds 20-30secs. Again unacceptable. I have investigated some feedback to gate current to try and achieve a crude constant power engine, but this proved very haphazard and overly complex.
Finally I came upon what I hope is a workable solution:
I have placed a very low Rdson PFET in parallel with Rsense. During the charge process when PG is not asserted the PFET is off and all current passes through Rsense which I have chosen to maximise charge current to a value which can peak at such a level as to allow the PROG set-point to be placed just at the minimum voltage of 0.4V to give the required power level to keep the pass FET well within an acceptable temp range by the end of the charge period. This is combined with a large Timer capacitance 47uF, that allows the 5-6 sec charge time to complete without fault.
When PG is asserted and after a short RC delay of just a few mS, I switch on the PFET, which hopefully at such low Vds will have a very predictable Rds value and can be used to set a much higher Ilim for the circuit when actively operating.
Still further to avoid being reliant on the PFET Rds on value, I have taken the IMON output to a comparator, which is set to trigger at a current level below that set by the PFET Rds on and used this output to trigger an OV state, thereby shutting down the pass FET, ( inverting the FLT output and feeding this back also to the OV input ensures this does not oscillate). In this way slowly rising current overloads are detected by the comparator and an appropriate filter to allow controlled over current timing, before shutdown. However under heavy load short circuit conditions Rsense (derived from the PFET) still current limits at a higher level than the comparator, which if the load is high enough drops enough voltage across the pass FET to cause PG to be de-asserted. This shuts down the PFET and places the circuit back into the lower Ilim state, in this state the output voltage collapses and the Timer capacitor begins to charge eventually triggering a fault condition.
Although not perfect, this seems to be the only way I can achieve my design goals.
I would ask you to consider for me the effect of using a PFET in this way, has this ever been done? I have simulated in TINA and I am quite happy so far with the results. I realise that the feedback from Rsense is sensitive and I am somewhat concerned that the addition of the PFET could destabilise the loop. However in reality the PFET should never experience large voltages and therefore its associated capacitance should have a negligible effect on the sense amplifier. I would value your feedback.
Included my TINA simulation.(Please visit the site to view this file)
All the best
Aidan
↧
↧
UCC28C42: UCC28C42
Part Number:UCC28C42
Hi All,
We have developed a AC-DC & DC-DC Board. We are having an issue of Voltage Drop when the load is connected to the board. There is drastic voltage variation in the board. It would be helpful if you can support for the same asap.(Please visit the site to view this file)
↧
TPS55340: TPS55340 power switch design
Part Number:TPS55340
Hi:
At present, a project product of our company uses three kinds of boost circuits, TL1963A (8.5V)+TL1963A (7.2V)+MP3426DL (21.0V). These three voltages do not work at the same time, but only one voltage works in the circuit at any time. Now, because of the layout problem, we want to save space, whether it is feasible to switch three voltages by PWM with TPS55340 chip, that is, input DC7.4. V voltage, through the following TI official schematic (demo board) in the case of constant capacitance and resistance and other related devices, whether the output of PWM signal through the single-chip microprocessor on the signal foot (SYNC) role, at any time to output any of these three voltages (8.5V, 7.2V, 21.0V).
Please reply in your busy schedule. Thank you. Thank you very much.
↧
TPS55340: TPS55340 design
Part Number:TPS55340
Hi:
At present, a project product of our company uses three kinds of boost circuits, TL1963A (8.5V)+TL1963A (7.2V)+MP3426DL (21.0V). These three voltages do not work at the same time, but only one voltage works in the circuit at any time. Now, because of the layout problem, we want to save space, whether it is feasible to switch three voltages by PWM with TPS55340 chip, that is, input DC7.4. V voltage, through the following TI official schematic (demo board) in the case of constant capacitance and resistance and other related devices, whether the output of PWM signal through the single-chip microprocessor on the signal foot (SYNC) role, at any time to output any of these three voltages (8.5V, 7.2V, 21.0V).
Please reply in your busy schedule. Thank you. Thank you very much.
↧
TPS65000: Dropout
Part Number:TPS65000
Hi,
We are using the TPS65000 in our design. Regarding the dropout voltage we only see in datasheet the 370 mV maximum for 250mA.
We would like to know the curve for the dropout voltage vs current and temperature. We have an Vin of 3.5V and a Vout of 3.3V in one of the LDOs with an output current of 150mA.
We would like to know that in order to know if we are within specifications.
Thanks.
↧
↧
TPS23758: Difference between TPS23758 and TPS23755
↧
TPS82084: TPS82084 minimum soft-start time
Part Number:TPS82084
I'm considering using the TPS82084 to supply a power rail that has a minimum ramp time of 0.2 ms. The TPS82084 datasheet lists a typical ramp time of 0.8 ms, but gives no minimum value. Please could you tell me what the minimum value is? If not, can you guarantee that it will be greater than 0.2 ms? I appreciate that the minimum value may depend on the characteristics of the load that it is supplying.
Many thanks for your assistance!
↧
UCC27282: H bridge bidir buck-boost configuration: bootstrap strategy ?
Part Number:UCC27282
Dear team,
I was wondering if you had an app note or a ref design somewhere that would use one of our HB driver in a buck-boost topology, without using a dedicated bias supply to provide the high side gate drive voltage.
I have worked on some ideas where we would use a few external passives for the switching HB to recharge the 100% duty cycle half bridge, but I am not sure it would work..
Many thanks in advance for your inputs!
Best regards,
PA
↧
UCC28180: PFC Mosfet Failure
↧
↧
BQ27426: Design Capacity write not working
Part Number:BQ27426
HI there,
We try to change the Design Capacity value in BQ27426 following the example in section 4.1 from SLUUBB0 document. We notice that:
- The flag readouts are the expected when the cfgupdate is toggled,
- the checksum is accepted by the IC (if we give wrong checksum the I2C packet is not acknowledged)
- and the configuration is read back (500mAh) right before soft-resetting and sealing the BQ27426.
Unfortunately, the FullAvailableCapacity() keeps returning the default 1296mAh, although the configuration is applied every time on MCU power up. We tried to power cycle the battery but it makes no difference.
Are we missing something? Is there an other configuration, not included in section 4.1, required for enabling new Design Capacity value?
Thank you in advance
↧
LM53601-Q1: treset_filter apply to VIN
Part Number:LM53601-Q1
Hi Team,
Does the treset_filter apply to VIN as well as the FB input?
For example, if my input voltage spikes low (say to 3.3V) very quickly and crosses the UVLO threshold (which can be as high as 3.55V), but the Vreset threshold is not crossed (which can be as low as 3.03V -> 92% of 3.3V output), the device reset can be asserted, but if this event is fast enough, can it be filtered out by treset_filter?
Thank you,
Jared
↧
CSD19538Q2: Pin 7 & 8
Part Number:CSD19538Q2
Hello,
Are pin 7 & 8 on CSD19538Q2 external pads that are connected to source and drain?
Thanks,
Joe
↧