Part Number: LM5165-Q1
Hi,
We are using LM5165-Q1 (SSOP) for a 5V design. However, we got 7.8V output regardless how the FB resistors changed.The schematic is based on Webench design. Currently, we have RT and ILM shorted to ground. HYS pin is floating and SS connected to a 0.056uF to grpund. Th einductor is 150 uH. as mentioned earlier, the output stay the same (around 7.8V) no matter how the feedback resistors changed. Thank you.
Best Regards,
Chun-Te Li
Part Number: LP8860-Q1
What are the default settings for BOOST_INITIAL_VOLTAGES[5:0] in EEPROM register 19? i.e upon first power up what is the output voltage of the LP8860-Q1
Part Number: UCC28950
Hi team,
I am writing this to check the UCC28950 shutdown timing sequence. Could you please check two questions below:
1. When SS/EN pin pulled below the VSS_STD threshold, does the internal logic terminates the existing PWM cycle immediately or it will finish the existing switching cycle and terminate the next switching cycle?
2. Do you suggest to disable the gate driver EN pin when fault event triggers? Is it safe to turn off the EN pin on UCC28950 and UCC27524 at the same time?
My customer has a concern if the gate driver EN pin was disabled during the switching cycle, the high di/dt on the magnetized X'FMR would cause high voltage spike and damages the FETs. Have you seen any cases like this before?
My understanding is that the difference between disabling and UCC28950 and gate driver UCC27524 when the fault triggers is that, the UCC28950 will complete the existing switching cycle and terminates the next PWM pulse, whereas shutting the gate driver will turn off the FET in the middle of duty cycle and that might cause similar to hard switching condition and potentially causing high voltage spike.
Thanks a lot.
Best Regards,
Wei-Hao
Part Number: TPS92602-Q1
Hi Support team
I am working on a customer application for an industrial camera. The issue I am having is the tps92602 is not responding fast enough to the frame clock and also to changes in the load conditions.
In the LED bank, one bank contains 8 leds in 4 sets (2 leds each set). THhy are using discrete fets to change the number of LEDS in the string for shadowing. The issue we are having is when we try to pulse at 120 frames per sec, the device is not responding fast enough. We are driving a string of 8 LEDS 4.2v each at 1.5~2 Amps. They may drive all 8 LEDS at once or just 2 LEDS via the switching network.
My two questions are is the the best part, I am using a dual because there are two different LED Banks? Second, is there a way I can speed up the response on the evm? They are testing boost to battery, they have a 12 volt input.
Thanks
Jeff Coletti
Part Number: LP2995
Hello,
Regarding TI Part number LP2995LQ/NOPB:
The operating temperature range for this component is listed as 0 to 125C in the datasheet. We need industrial (-40C) if possible. We have a few questions.
Does TI have qual data to indicate expected performance?
Could TI screen parts?
What is fault if operated below 0C temperature limit?
Thanks,
Doug
Part Number: LM5145
Hi
I'm using the LM5145 for my buck converter. It looks like that at light load the switch off timing of the high side FET is too slow.
Please check the attached pictures.
CH1: Vds, CH2: Gate low side, CH4: Gate high side
As you can see the behavior is ok during the switch on of the high side FET. Low side gate goes low and after the dead time, the high side gate goes high. Everything ok.
BUT during the switch off of the high side FET, it looks like that the high side gate takes to much time and than the low side gate switches on. There is no dead time.
If I increase the load, it looks better.
Can you explain me that?
BR
Silvano
Part Number: TPS92691
Hello,
I have designed a Buck connverter with the TPS92691 driver.
Vin = +18V to +26Vdc, Vnom = +24Vdc
Vo = 5Vdc (that is the Vf tipycal led value used as a load)
Io = +4.5Adc.
My doubt is about the correct values for Rls2, Rls1 and the zener diode used in the output stage of the converter. (Schematic R1, D1 and R7).
The datasheet only describes that this values can modify the time raise and fall for when a P-FET is used, which is my case. The schematic is as it is described in page 18.
The zener diode is used in the examples described in the datasheet.
I know that this is a bit dependant of the mosfet selected, but what is exactly the goal of this network to desing the adequate values? What's the correct way to design this network?
Another thing that I want to know is if that can produce a change in the output current when pwm dimming frequency is changed.
I mean, if and improper design of this network can produce this issue.
As far as I know changes in pwm dimming frequency should not change the output current value, only the duty cycle would produce it.
Regards,
Part Number: LMG3410-HB-EVM
Hi,
I am looking into a interesting fact of LMG3410-HB-EVM: The !FAULT output is routed to adjust the slew rate of low-side FET. What's the consideration under this design?
Peiheng.
Part Number: TPS54360B
Hi, all
I have a question. Where is the date of production coded? Is there any document describing the letters from the 3 lines.
A)
1 line: 54360C
2 line: TI 91A
3 line P20EG4
B)
1 line: 54360C
2 line: TI 91A
3 line P20GG4
Part Number: TPS56637
When might the TPS56637 be released? Any chance of a SOIC-10 package?
Part Number: UCC27211
Hello,
I am using 3x of the UCC27211 to run a 3 phase motor and am trying to use an isolated power supply for the high side rather than bootstrapping the VDD.
I am using a modified version of this reference design : http://www.ti.com/lit/df/snvr323/snvr323.pdf
My version creates 3x ~14V supplies on the secondary side and one 10.2V supply from the LM5017 on the primary side
Flybuck schematic:
Gate Driver schematic (single phase):
I am finding that a lot of the time either my gate drivers or the LM5017 will fail while switching the MOSFETs while driving a motor. The voltages on the transformer are pretty constant, but I was wondering if there is a possibility that the bootstrap diode within the gate driver is conducting due to some weird transients? The LM5017 failure manifests itself in a hole melting into the VIN pin and the gate drivers usually fail with some pins shorted to VDD or GND (not consistent)
I've run with a thermocouple attached to my gate driver and the LM5017 and have not noticed any gradual overheating.
Are there any problems associated with choosing not to bootstrap from VDD and using an isolated supply at the HB pin instead? VCC_hiside_U (HB pin) is ~14V while VCC_lowside (VDD pin) is 10.2V so the diode should be reverse biased.
Thanks,
Vishaal Varahamurthy
Part Number: TPS61193
The datasheet says that, "The VDDIO/EN pin provides the supply voltage for digital IOs (PWM and SYNC inputs)and at the same time enables the device." I'm not quite sure what that means. Does it mean that there are an internal pull ups for the digital inputs, or do pullups have to be provided externally? If no internal pullups, does the LDO output appear on the LDO pin? If so, I'd like to steal a few microamps to create a digital supply for the pullups. Does the PWM pin need a pullup for maximum brightness, or can it be left unconnected?
Thanks
Part Number: TPS549A20
Hello E2E,
I want to confirm a few questions about the TPS549A20:
Soft-start:
Per table 12, the default SS time is 1ms, correct?
What is the min and max?
Pgood:
The default PGood time is 1ms, correct?
What is the min/max on this spec? It appears that this closest data in the electrical characteristics table shows min; typ; max as 0.819; 1.024 ;1.228. Would I be safe using those as the default min/max values?
Thanks!
Russell
Part Number: TPS61252
After working with a new prototype for 15-30 minutes or more, the shutdown current starts to rise. At first, it was ~1uA, then it was 40uA, then it continued to climb and now it is consuming 4 mA in shutdown mode. This is the second prototype that exhibits this type of behavior. The first prototype was as high as 10 mA shutdown current and pretty much stayed around there. I went so far as to remove every component from the prototype, leaving just the TPS61252, in order to determine that it was the source of the current draw.
I can think of a few things in my design that can be improved but I allowed them so that I could more easily fit components in the available space. I never suspected that making these compromises might cause a shutdown current malfunction. Can someone please evaluate my design and tell me if a glaring error is discovered.
Here is the schematic:
I measured voltages while the device is in shutdown:
I also removed the inductor so that Pin 7 is not connected and this did not solve the problem. So the leakage current is coming from Pin 8.
I don't think that the schematic has any issues. It must be the layout. My biggest mistake (probably) is the PCB stack-up. It has 4 layers with a ground plane and a power plane. The power plane is directly beneath the TPS61252, not the ground plane. Also, the footprint contains thermals which "choke" the ground pour a bit, potentially causing more issues with the ground path.
Here is a picture (mirrored because it is a top-view of the bottom layer):
I can send gerber files if needed.
About to receive a third prototype tomorrow that I can test. If you have any recommended steps to test this prototype, please advise.
Regards,
Seth Berggren
Part Number: BQ25710
Hi all,
is there any information available on how to tune the compensators for this charger? We have used the default values from the EVM board and there is too much jitter in the converter operation.
Thank you
Part Number: BQ40Z60
We are designing a pack using bq40z60, and want a feature that the pack can Auto shutdown when SMBus both lines are pulled low for 2 seconds.
I noticed that there is a auto sleep mode but it only turn off charge FETs, not discharge FET.
There is a Auto ship mode can be active but it turns off both FETs in a minute.
Is there anything else I should set to allow discharge FET being turned off when SMBus both lines are pulled low for 2 seconds? or few seconds but much less than a minute?
Thanks,
Zane
Hi,
My customer is looking for a buck supply that can take 8-19V in, and provide up to 5.2V @ 1.5amps. The tricky part is that the load is down 2.8 meters of 26AWG cabling (3 strands 26AWG for V+ going to the load and 3 strands of 26AWG on GND coming back from the load) and they want to compensate for cable drop. As the load increasing the buck has to regulate to a higher output voltage to compensate for voltage drop from the resistance of the cable. I have seen a couple post point to the following article showing how to to compensate for cable drop with an INA but I was hoping that this has been simulated before in TINA.
https://www.eenewspower.com/content/how-extend-power-supply-droop-compensation
They are looking at the LM27341 buck converter but want to be able to simulate the circuit before putting it on their board. Is this possible? Is there a starting point that someone has done in the past?
Ultimately they are open to any TI buck and want a solution that is cheaper than the LT6110 device that expensive. Therefore if there is a recommendation for a different Buck other than the LM27341 that is better suited for this application, please let me know.
Thanks!
John
Part Number: TPS745
Hello,
Can you please confirm or clarify the following about the TPS745-Q1 adjustable option?
Thanks,
Alan Ocampo
Analog Field Applications
Texas Instruments Inc.
Part Number: TPS7A78
Hi
Could you please let me know your recommended Rs/Cs value for the following conditions?
Also, how will we select those values?
ACin = 80Vac ~ 276Vac
Bridge : Half bridge
Muk
Part Number: UCC27525
Hello,
I'm using a UCC27525 gate driver IC to drive the mosfets being used in the CUK converter topology attached below. A dual mosfet is being used with a NMOS and a PMOS integrated in it. My question is that what is the safe voltage range for the VDD pin to be supplied with? What i supply the VDD with is a +8v. To drive the gate of a PMOS a negative pulse should be applied to the gate and that's why i used an extra circuitry other than external gate resistor circuits as shown in the file attached below. But the problem is that as the supply voltage applied to VDD pin goes up, the inductor current and output voltage waveforms become pretty noisy. The most stable voltage current waveforms were yielded with a +8v supply voltage and below(Please visit the site to view this file).
Secondly, what is the value of RNMOS for this gate driver IC. Based on the datasheet the effective resistance of the hybrid pullup structure during turn on is estimated to be approximately 1.5 × ROL, estimated based on design considerations. Where is this resistance used for in IOH calculation?
Third, what is the internal operating frequency of the gate driver IC?