Part Number: TPS92518HV
There is another behavior I can't figure out.
If the last command to the 92518 was a write (specifically to Toff[MAX]), then at some point after I don't talk to the device, the SPI Error bit gets set.
However, if I read the status register last, then SPIE does not get set.
To describe this in more detail. I'm writing some python that talks to four TPS92518HVs through four 32 bit registers within an FPGA I designed that has a SPI controller in it.
To keep things simple, I do all transactions 16 bits at a time. Write commands were being sent twice and I grabbed the reply data from the first write to ensure that the transaction went according to plan.
Doing things that way caused the SPI error bit to be set when I polled them again some seconds later.
When I changed the sequence to be a write of the desired register followed by a read of the status register, the write response frame arrived, but the SPI error bit does not get set.
It seems as if the device requires the write response frame to be trasfered or a SPI error occurs.
If that's not what's happening, what rule am I violating?
More importantly, is there a better way for me to access the part? Is there a NOP command that will let me fetch the response frames?
Thanks much.
