Part Number: UCD3138
OK, here is the case. I have used a UCD3138A in a three level buck converter. The controller regulates the output voltage with dual loops, a current loop inside monitoring inductor current (AFE2+Filter2+DPWM2) and output voltage outside monitoring the output voltage (AFE1+Filter1+DPWM1).
According to the simulation, the input voltages on the input capacitors, series connected, have to be balanced with tuning the duty cycles of buck switches. We have now trouble and questions on the use of current/voltage/flux balancing function of UCD3138A.
In the manual sniu028a I have found several places for cycle adjustment for balancing current/voltage:
- The LOOP MUX cycle adjustment register, CYCADJCTRL and related regs. But according to the manual, the cycle adjustment output is based on the error of the two AFE inputs. That means only a proportional compensation is injected into the DPWM duty cycles which also means the static error exists on the voltage balancing.
- The DPWM cycle adjustment A and B registers, DPWMCYCADJA and DPWMCYCADJB. I did not found any information that these two registers can be automatically updated from any output of filter0~2. To have them updated automatically is preferred in my case so I could use the CPU resources for many other functions.
At present my plans is: I use another filter (filter0) as the voltage balancing compensation.The error of two input voltages, vc1 and vc2 are sensed in AFE0 and compensated in Filter0. The output of filter0 could be used as duty adjustment to fix the unbalanced vc1 and vc2. The compensated DPWM0A and DPWM0B are used to driven the two switches of Buck.
The configuration is shown below.(I made a mistake the DPWMCYCADJB=-YN)
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I use the timer interrupt programa to updated the DPWMCYCADJA and DPWMCYCADJB by reading filter0 outputs. (But I still would like them to be updated automatically instead of CPU interrupt. ) The principle of voltage balancing in this case is to assign DPWMCYCADJA with a positive filter0_output value while DPWMCYCADJB a nagetive -filter0_output value to fix the unbalanced voltage. In the present experiments, I found the duty cycle shrinking very badly when load is light and input voltage low. I have tried many filter coefficients and bandwidth in voltage¤t open loop but the results are not satisfied. The interrupt frequency(around 100kHz) shows a little lower than the configured frequency (T16 timer, 250kHz). Only a few lines of reading and assignment codes are written in the interrupt programa. So
- I wonder if there might be some reason for unstable interrupt frequency that causes the duty cycle shrinking?
- If there is an idea or configuration to have the two registers updated automatically?or any other applications on current balancing for me to refer.
I also have a backup plan. For the first plan above I only used one single DPWM0 to generates two phase shifted PWMs. I still have one DPWM module free (DPWM3). So if I modified the DPWM structure to use two modules, both DPWM0 and DPWM3 to generate two PWM signals, I wonder if the trouble could be solved? The key issue is, how to automatically inject one filter output (filter 0) to two DPWM modules of duty cycles with opposite polarity. (PWM1B duty cycle value =filter1+filter0, PWM3B duty cycle value=filter1-filter0)
OK, if the above plans do not work,,,,,,,I also found the feedforward function in the LOOP MUX . But this function is very wired in the chip because the feedforward is configured to multiply two filter outputs as one to eliminate the high transient of input voltage instead of summation…the traditional feedforward is a summation of inputs...
OK, if the above plans do not work…again… I have to use the CYCADJCTRL in the LOOP MUX. I wonder if the compensation could be injected into one DPWM module with opposite polarities?or do I have to use two DPWM modules? Any reference coding I could look up for this similar application?
I also listed my preferences here:
Firstly I prefer the cycle adjustment to be updated automatically by DDPs.
Secondly, I prefer to eliminate the static error of the voltage balancing.
Thank you very much!