Part Number:LP38693-ADJ
Hi All,
== ISSUE
On power up, Vout has output around 50ms even when EN signal has been held low.
== BACKGROUND
Currently using three (3) LP38693-ADJ chips on a board, all adjusted to 1.5V output, Vin is 3.3V.
EN signal is held low on power up and driven high when the FPGA on the board has finished loading the bitstream. This signal from Oscilloscope looks good.
However, when 3.3V is powered up, the Vout has around 50ms output voltage around 0.5V for two (2) of the chips, and one (1) of them has an output of 1.2V for 50ms.
Two (2) of the LDOs are supplying power to the FPGA IO bank, and the other one (1) is supplying power to some 1.5V to 3.3V level shifters.
Please help this issue.
Thanks,
Albert