Part Number:CSD95378BQ5MC
Hi,
A customer of mine is using already the CSD95378BQ5M in a design. They wonder what are the main differences with the CSD95378BQ5MC?
Can they use the CSD95378BQ5MC as a direct replacement for the CSD95378BQ5M?
Thank you in advance!
Part Number:LM27964
Hi TI,
Could you recommend a right part?
I need I2C control for high frequency PWM output. (over 300kHz)
hai,
is there any TI ICs that can take 9-36v input and provide 5v and 12. its not mandatory that a single ic should give both 5v and 12v. the ic that give 5v out should provide at least 6A current, while 12v ic should provide 2 or 3A current. is there any with above spec that have EMI EA 55032 class A & FCC level A approved?
Part Number:TPS61099
I HAVE TO MAKE A DESIGN IN WHICH I NEED A REGULATED OUTPUT VOLTAGE OF 3.3V OR 5V
INPUT : 0.7 TO 5 VDC (VARIABLE) 10 W (MAX)
OUTPUT : 3.3V OR 5VDC (2W )
I AM NOT ABLE TO FIND SUCH A DC DC CONVERTER.
PLEASE HELP ON THIS DESIGN
Part Number:TPS24750
According to data sheet, the gate capacitor Cgate is calculated by equation 15. An intrinsic capacitor Cintrs is deducted from the first term. In the text above, the value of Cintrs is stated to be about 175pF.
In the design tool (TPS2475x_Design_Calculator_LowVin_Rev-.xls), Cgate is calculated in line 71. There, this Cintrs is a totally different value, calculated from (22nC / 5.8V), values taken from lines 24 and 26, respectively. That equals to 3.8nF. As a consequence, my intended slew rate of 10V/ms (leading to 0.5A loading the output capacitor of 50µF) even leads to a negative Cgate.
Since a reasonable result is achieved by the example of using 4.7nF as Cgate in the data sheet (measurement in figure 44), I think that the design tool is wrong.
Could you please advise as a quick fix if I just can use the 175pF for the second term in line 71 of the design tool, or is there a more global error with the gate charge of 22nF (line 24)?
One note to the accuracy of the dV/dt control. Looking at the measurement of the example in the data sheet (figure 44) it seems that the actual output slew rate is about twice as high as expected (expectation would be 7V/ms according to equation 15 and assuming 175pF is correct). Does it make sense to correct the calculated Cgate by this empiric factor of 2 (means use twice the calculated value), or is there just a large variation of FET parameters in the production of the device?
Part Number:TPS54540-Q1
Hi everyone
I am using a TPS54540 IC as the main buck converter in my system(to decrease 13 V to 5 V). Also, the system contains AM radio which its frequency band is 522 kHz- 1610 kHz. So, The TPS54540 switching frequency should be above 1.8 MHz. The TPS54540 delivers 5 V, 5 A properly when Fsw=1 MHz. But, when I increase the switching frequency (above 1.8 MHz), it can not deliver 5 A (it delivers 4A). As the current goes more than 4 A, large ripples appear on the output voltage which its frequency is under 10 kHz.
I wonder, does this IC can deliver 5 V, 5 A when the switching frequency is above 1.8 MHz without such ripples or not?
I appreciate any help in advance.
Armin
Part Number:TPS24750
I need to delay the turn on/off operation such that at Vcc rising, turn is is delayed and otherwise turn off is also delayed when Vcc is falling (of course the UVLO is applicable in parallel).
I want to achieve this by connecting a capacitor (of the order of 100nF) between GND and the EN pin, while R1 (between VCC and EN) is of the order of 100kOhm, and another resistor is in parallel to the capacitor (between EN and GND). By this, the standard resistor divider (for this application, separate from the OV resistor divider), just with an additional capacitor.
This can lead to EN having still a voltage applied (due to the charge of the capacitor) which VCC already has fallen below the voltage at EN. The data sheet does not specify this situation.
VCC is 3.3V nominal. Could a voltage of 3.3V at the EN pin, while VCC is 0V, damage the device? In case, would damage be prevented by using an additional resistor between the resistor divider/capacitor and the EN pin, to limit a current that may flow e.g. via protection diode within the device?
Part Number:TPS92691
Dear support team
According to the DS Figure 26 der PNP transistor for the OVP is connected as following:
Base -> Input/LED-
Emitter -> [Res.] -> Output/LED+
Collector -> OVP
However in the design example Figure 41, the connection is as following
Base -> Output/LED+
Emitter -> [Res.] -> Input/LED-
Collector -> OVP
Is the connection in Fig. 41 wrong or why is the bipolar in the design example connected differently?
Thanks and best regards
Raphael
Part Number:BQ25895EVM-664
HELLO,
I bought the BQ25895EVM-664 and trying to get know the charger(BQ25895) settings.
but at the program there is a lot name shortcuts witch i cant find any explanations for them .
second, is there any guide to integrate between the charger and the batterys fuel gauge?
BR,
MICHAEL
Part Number:TPS717
We test the TPS717 input voltage is 5V, and output is 1.8V. The output load transient is 0A to 400mA as like the system load. We find the output voltage raise up during over current. As I know the voltage should be drop down. May I know why the voltage going up?
In addition. I know the TPS717 maximum current is 150mA. May I know the TPS717 can support an over current during short time pulse?
BR,
Gary
Hi,
I am using TLV70033 LDO in on of my design, where this LDO is used for powering MCU.
I have noticed many times my LDO heats up due to shorting of MCU power line.
I don't understand the reason behind the MCU shorting. As per my understanding LDO's overshoots nature might harm MCU.
In front of LDO it is powered by TPS54260 with 12V to 5V conversion and its 5V is given to LDO. At input side of LDO we have used 10uF and 0.1uf ceramic caps and at output side 0.1uF, 10uF and 47uF caps are kept.
Please help me out in debugging this problem.
Part Number:BQ34Z100
Dear TI,
What is the best choice for monitoring the full charge capacity of Lead-acid batteries up until 100Ah.
BQ34Z100-G1 (Impedance Track)
BQ34110 (CEDV gauge)
I do not see an evaluation module for the BQ34Z100-G1, only one for the BQ34Z100 which doesn't support lead-acid.
Does the Bq34z100EVM also support lead-acid batteries?
Remko
Part Number:BQ34110EVM-796
Hi,
We are trying to make a new .fs file for an upto date calibration with an official battery pack that will be used for the production unit.
Hi,
I programmed the BQ34110EVM-796 using BQStudio (1.3.54.1) with .fs file (see attached) and EV2300 (version 3.1m). The programming failed at some point, not sure what happened and the BQ34110 got stuck in ROM mode. Before programming with BQStudio, the pins of the BQ34110 chip were:
REGIN = 2.6V
REG25 = 2.5V
BAT = 400 mV
CE = High
VEN = High
The file I sent is the same we used on lots of units before without any problem. However, REGIN was below 2.7V, so it might be why the programming failed. On our units, the design insures REGIN is above 2.7V.
After that, I was able to communicate with the BQ34110 on the ROM mode address using the Advanced Comm tab (ex: read at 0x16 00 without error). Since the device was already in ROM mode, I modified the .fs file to remove the “Unseal device” and “Go to ROM mode” steps. I tried to send the .fs again, however the EV2300 did not send any command on I2C when programming the .fs file (checked with sniffer on i2c lines). I closed and reopened BQStudio and selected “0110_0_02-bq34110.bqz”.
To make sure REGIN > 2.7V, the J2 jumpers were modified to have:
REGIN = 4.6V
REG25 = 2.57V
BAT = 400 mV
CE = High
VEN = Low
Then, the programming worked until line 42 of the attached file, which is a compare flashstream command:
C: 16 04 3B 8C FE FB
With the sniffer, I saw that the data read on BQ34110 was not 3B 8C FE FB, that’s why it stopped. Unfortunately, I did not keep the sniffer data…
I was not able to get out of the ROM mode (tried sending W: 16 00 0F and W: 16 64 0F 00 and reset the BQ34110). I removed 4 compare commands that began with C: 16 04 <data> and programmed the .fs again. BQStudio was able to send the whole file, but now the BQ34110 nacks at both addresses (0x16 and 0xAA) even after a reset, so it seems I bricked it.
The pins states are still:
REGIN = 4.6V
REG25 = 2.57V
BAT = 400 mV
CE = High
VEN = Low
My questions are:
Thank you,
Part Number:TPS54620
Please help check if there is a problem with the circuit schematic of TPS54620, TPS54521, and TPS24701?
Or Show us how to check the circuit schematic.
After the entire schematic design of the circuit is completed, it is necessary to detect those parameters and recommend which software to detect;
Thanks A lot.
Part Number:TPS65311-Q1
Hello,
I am considering using a TPS65311-Q1 for my PMIC but I have some questions on its capability. I have an FPGA-based standalone design with +24V input and need to create 5 voltages: +5V, +3.3V, +1.8V, +1.2V, +1.0V. The part has an SPI interface, but this application is standalone. By my read of the datasheet the SPI interface provides mostly error status.My main concern is on supply sequencing. Figure 24 on p. 32 shows the sequencing, but how is it controlled? Do I have to pick which voltages go on which regulator to get the sequencing I need? How is sequencing controlled? If the SPI interface is needed, can I set the values there and will they be retained after power cycling?
Mark
Part Number:LM2704
Hello.
I am a newbie in DC/DC design, so have some problem with LM2704. Design requirements:
Input voltage -- 3,3 V
Output voltage -- 12 V
Output current -- 40 mA max.
Output load -- 2 relay coil, 20 mA per one.
Main purpose of this design -- generate voltage to control two 12 V relay coil from 3,3 V powered CPU. Circuit on Figure 6 in datasheet was used as reference .
After checking on real PCB I see some strange behaviour of output voltage. Both relay are ON -- otput voltage is 12V. One relay ON, other relay OFF -- 16 V on output. Both relay are OFF -- voltage jump to 30 V. May be I missunderstand LM2704 datasheet, and this IC work only as current source for LED's ? What DC/DC IC in SOT-23 package in this case suitable for my requirements ?
Circuit with used parts designation in attachment.
Best regards, Volodymir.
Hello Experts,
We'd like to build/procure? a power supply for a simple device we envision. Have done quite a bit of work on the embedded side, usually with pre-existing power solutions in place, but have never built a power supply ground up. Do we even need to? Frankly, I'd like some advice on how complicated this needs to be!
Upstream: power will be standard AC 'household' current; ideally the entire range from 115 through 230VAC.
The entire power load will be in the 3.3V MCU range. The circuit it will drive will be very low load; in fact, we'd like to avail ourselves of the MCU's low power mode, while keeping it responsive.
As the design will include one or more radio protocols - Bluetooth? TI 15.4?, I imagine the EMI noise factor will come into play.
Early research points to integrated monolithic transformer/regulator units, ready for solder, mostly non-TI. Would one of these be the way to go? I've begun to look at TI's Power Designer, but one can get in very deep very quickly here...
What are my next steps in terms of research - or can someone here point me to specific devices?
Part Number:TPS2493
Tool/software:TINA-TI or Spice Models
Hi,
The TPS2493 datasheet describes the function of the PG open drain output pin. It states that the !PG pin will be open drain whenever the external FET Vds is > 2.7V, or UVEN is low or UVLO is active. It also then explains the 9mS deglitch timer. The block diagram of the IC shows that the 9mS deglitch is after the comparator which is monitoring Vds, whereas the UVLO and UVEN are inputs which control the enable of the fault logic circuit.
My question is this:
When I simulate the action of pulling low UVEN whilst the TPS2943 is active and the !PG pin is low (OUT has reached the VCC voltage), at the point at which UVEN goes low, !PG stays low for a further 9mS. Is this actually correct? The block diagram does not indicate entirely clearly how the !PG NFET is managed by the fault logic. The TINA model seems to indicate that the same 9mS de-glitch delay is also associated with changes detected at the UVEN pin and I assume also UVLO. The wording of the datasheet infers that all events that might cause !PG to go open drain are associated with the de-glitch circuit and regardless of the action which triggers !PG to go open drain there will always be 9mS of delay on the !PG pin. The TINA model reflects this inference.
Can you please clarify that this 9mS timer is seen with all events that cause !PG to go open drain.
Thanks
Aidan